1. Technical Field
This invention relates to the field of transistor gate conductor structures in semiconductor devices. More specifically, the invention relates to a method for forming borderless gate structures and the apparatus formed thereby.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in complimentary metal-oxide semiconductor (CMOS) technologies, such as in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.) One feature that increases device density is a "borderless contact." To explain the significance of a borderless contact, one example of a defective wafer portion 400 is shown in FIG. 3 having a partially formed FET on semiconductor substrate 480 between isolation areas 490. When a contact hole 410 for a diffusion contact to a diffusion area 420 is opened through a passivation oxide layer 430, it may expose a portion of a gate conductor 440 to contact hole 410. Even though sidewall spacers 450 protect the side of gate conductor 440 from shorting, if a diffusion contact were formed in contact hole 410, then it may easily short to the top of gate conductor 440. Accordingly, a contact border, as shown on wafer portion 460 in FIG. 4, is often used to prevent shorting between gate conductor 440 and diffusion contact 470. In wafer portion 460, the contact hole in which diffusion contact 470 is formed is shifted away from gate conductor 440 to create a border of passivation oxide 430 between gate conductor 440 and diffusion contact 470. The contact border thus reduces the potential for diffusion contact 470 to short to gate conductor 440. Unfortunately, the use of such a contact border expands the area needed for FETs, consuming a great deal of chip area and preventing further increases in circuit density.
As described in IBM Technical Disclosure Bulletin, Vol. 32, No. 4A, September 1989 (MA888-0005), current technology provides for the fabrication of a silicon gate conductor such that diffusion contacts may be formed without borders, that is, borderless contacts may be used. Referring to FIG. 5, a wafer portion 500 is shown having a semiconductor substrate 580 with isolation areas 590, a gate oxide layer 530, a silicon gate conductor material layer 540, and an etch-stop dielectric film layer 560 formed thereon. Etch-stop dielectric 560 is not used in a typical silicon gate process for forming transistor gate conductor structures. However, use of etch-stop dielectric 560 provides the opportunity to increase device density by forming borderless contacts to diffusion areas. Unfortunately, the method of protecting gate conductors with etch-stop dielectric 560 possesses several limitations. For example, after formation of gate structures, gate polysilicon is typically doped by implantation to decrease sheet resistance at the same time the source and drain diffusion areas are implanted. In some circumstances, the presence of etch-stop dielectric 560 on top of a gate structure is sufficient to preclude such a single implantation step. Accordingly, gate conductor material layer 540 in FIG. 5 must be implanted before depositing etch-stop dielectric film layer 560 and a separate implantation step for diffusion areas will occur after formation of gate structures. More importantly, selective metal silicide, such as CoSi.sub.x or TiSi.sub.x, is typically formed in the surface of source and drain diffusion areas and gate conductors in a single step after the implantation step. If etch-stop dielectric 560 is used, then selective metal silicide must be formed on gate conductor material layer 540 after it is implanted, but before depositing etch-stop dielectric film layer 560. A separate step of forming selective metal silicide in diffusion areas will occur after implanting the diffusion areas.
To form a wafer portion 600 as shown in FIG. 6 from wafer portion 500 in FIG. 5, gate conductors and interconnects are defined in the stack of gate oxide layer 530, gate conductor material 540, and etch-stop dielectric 560, leaving the top of each gate conductor covered with etch-stop dielectric film layer 560. Next, sidewall spacers 650 are formed on the sides of gate conductor 540, encapsulating gate conductor 540 in dielectric, and diffusion areas 620 are implanted. Passivation oxide 630 is formed over the structures and contact holes formed therein for diffusion contacts (not shown). Notably, gate conductor 540 is covered on the top with etch-stop dielectric 560, thus, the encapsulating material will remain after the contact hole etch. FIG. 6 shows diffusion contacts 670 formed in contact holes, wherein no contact border is needed to prevent shorting between diffusion contacts 670 and gate conductor 540. Instead, etch-stop dielectric 560 is in place to prevent shorting and device density is increased since the contact holes were shifted closer to gate conductor 540.
Therefore, there existed a need to provide a method of fabricating borderless contacts that is compatible with current silicon gate fabrication processes.